Orthogone Technologies Launches Ultra-Low-Latency FPGA IP Portfolio for Multi-Industry Deterministic Networking

Orthogone Technologies, a multidisciplinary engineering firm specializing in embedded systems, hardware, software and FPGA solutions,  announced the availability of its Ultra-Low-Latency (ULL) FPGA IP Portfolio, a suite of production-grade networking and data-movement IP cores for AMD (NASDAQ: AMD) UltraScale+™ and Versal™ adaptive platforms, extending its proven FPGA technology to engineering teams across a broader range of industries.

Originally developed for FinTech applications, where performance, determinism, low jitter and reliability are critical requirements, the technology behind the portfolio has been deployed in production, supported and refined over several years. Orthogone is now making this proven Field-Programmable Gate Array (FPGA) technology available to customers in other demanding markets, with early adopters already using the IP cores beyond FinTech, including in aerospace and defense, as well as quantum computing applications.

The Portfolio at a Glance The portfolio packages Ethernet MAC/PCS with optional Reed-Solomon FEC, hardware TCP/IP and UDP/IP offload engines, and a PCIe® circular-buffer DMA controller into a single, integrated development kit, letting embedded teams add deterministic, sub-microsecond-class networking and high-throughput packet processing to their designs without building protocol logic from scratch. By offloading network processing to the FPGA, the portfolio reduces the packet-processing workload on the host CPU, freeing compute resources for other application tasks.

The Ethernet MAC/PCS cores deliver standards-compliant IEEE 802.3 Ethernet at 1G, 10G, 25G, 40G and 100G line rates with optional RS-FEC at 25G and 100G. The TCP/IP and UDP/IP Offload Engines move Layer 2 through Layer 4 processing into FPGA logic, delivering full throughput with best-in-class latency performance. Additional features and data rates for these cores are available through a custom technical-commercial engagement with Orthogone's engineering team.

The PCIe® Circular-Buffer DMA controller provides bidirectional data movement between the host and FPGA over PCIe Gen3/Gen4.

From FinTech-Proven Performance to Multi-Industry Applications Orthogone's ULL Portfolio brings these capabilities to engineering teams across data center and high-performance computing, aerospace and defense, industrial and robotics, medical devices, communications, test and measurement, quantum computing and other compute-intensive applications — anywhere throughput, latency, jitter and FPGA resource efficiency all matter at once.

The portfolio ships as an integrated kit including encrypted RTL source, reference designs for AMD Alveo™ boards, end-to-end simulation testbenches, a complete Linux driver stack, and product documentation. Orthogone offers project, site, corporate, annualized and card-based licensing options.

"This portfolio brings together IP originally built for some of the most latency-sensitive systems we work on. It has been deployed in production and supported for several years," said Alexandre Raymond, CTO of Orthogone Technologies. "It provides teams in other industries with a proven, integrated kit they can build on without starting from scratch."